mb9b400a series 32 - b it a rm ? cortex ? - m3 fm3 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 05610 rev. *e revised october 2 4 , 2017 the mb9b400a series are a highly integrated 32 - bit microcontroller that target for high - performance and cost - sensitive embedded control applications. the mb9b400a series are based on the a rm ? cortex ? - m3 processor and on - chip flash memory and sram , and peripheral functions, including motor control timers, adcs and communication interfaces (can, uart , csio , i 2 c, lin). the products which are described in this data sheet are placed into type 0 product categories in "fm3 f amily p eripheral m anual ". features 32 - bit a rm ? cortex ? - m3 core ? processor version: r2p0 ? up to 80 mhz frequency operation ? memory protection unit (mpu): improve the reliability of an embedded system ? integrated nested vectored interrupt controller (nvic): 1 nmi ( non - maskable interrupt) and 48 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [flash memory] ? up to 512 k byte ? read cycle: 0wait - cycle@up to 60 mhz, 2wait - cycle* above * : ins truction pre - fetch buffer is included. s o when cpu access continuously, it becomes 0wait - cycle ? security function for code protection [sram] this series contain a total of up to 64 kbyte on - chip sram. this is composed of two independent sram (sram0, sram1). sram0 is connected to i - code bus and d - code bus of cortex - m3 core. sram1 is connected to system bus. ? sram0: up to 32 k byte ? sram1: up to 32 k byte can interface (max. 2 channels) ? compatible with can specification 2.0a/b ? maximum transfer rate: 1 mbps ? built - in 32 message buffer multi - function s erial i nterface (max. 8 channels ) ? 4 channels with 16steps 9bit fifo ( ch.4 - ch.7), 4 channels without fifo ( ch.0 - ch.3) ? operation mode is selectable from the followings for each channel . ? uart ? csio ? lin ? i 2 c [uart] ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generator ? external clock available as a serial clock ? hardware flow control: automatically control the transmission by cts/rts (only ch.4) ? various erro r detect functions available (parity errors, framing errors, and overrun errors) [csio] ? full - duplex double buffer ? built - in dedicated baud rate generator ? overrun error detect function available [lin] ? lin protocol rev. 2.1 supported ? full - duplex double buffer ? master/slave mode supported ? lin break field generate (can be changed 13 - 16bit length) ? lin break delimiter generate (can be changed 1 - 4bit length) ? various error detect functions available (parity errors, framing errors, and overrun errors)
document number: 002 - 05610 rev. *e page r i 0 % % $ 6 h u l h v > , & |